Traditional reverse protection circuits typically use PMOS transistors.

Connect the resistor of the PMOS's gate (G) to ground (GND). When the input terminal is connected to a positive voltage, current flows through the body diode of the PMOS to the load terminal.

If the positive voltage exceeds the threshold voltage of the PMOS, the main channel conducts. This reduces the Vds voltage drop of the PMOS, and the current flows through the main channel, achieving low loss and low temperature rise.

Traditional PMOS Reverse Protection

In this circuit, the voltage at both ends of the MOS, i.e., the voltage drop across the body diode, is greater than the VGS voltage of the MOS transistor, so the MOS transistor conducts, shorting the body diode. The voltage drop across the body diode no longer exists.

R1 is the current-limiting resistor for the LED in the voltage divider. When conducting, the LED lights up, indicating that the power supply is connected correctly.

When the power supply is reversed, the voltage at the GS terminals of the PMOS is positive, and the MOS transistor cannot conduct.

Rg reduces the pulse current and voltage division when the NMOS conducts.

When the voltage at the GS terminals is too high, the Zener diode D enters the reverse breakdown mode. Within a certain range of reverse current, the reverse voltage does not change with the reverse current. When the input voltage is too high, Zener diode D can prevent the voltage at the GS terminals from exceeding the rated value and damaging the MOS transistor.

It is important to note the orientation of the MOS transistor's body diode. When the body diode faces Vin, once reversed, the current will flow from GND to the body diode to Vin, causing a direct short circuit, which will not prevent reverse connection.

However, using PMOS as a reverse protection circuit has three drawbacks.

One is high standby current:

There will be dark current losses in VGS driving and protection circuits, both of which are composed of the Zener diode and the limiting resistor R, and the limiting resistor will affect the entire standby power consumption. If the value of R is increased at this time, the Zener diode will not reliably conduct, and there will be a risk of overvoltage in VGS, which will also affect the switching speed of the PMOS.

Another is the existence of reverse current:

During the input voltage drop test, the PMOS remains conducting when the input voltage drops, and the voltage across the capacitor will cause the polarity of the power supply to reverse, leading to a system power failure and interruption.

The last is the cost issue:

We all know that the cost of PMOS is relatively high, so PMOS is generally suitable for scenarios with currents exceeding 3A.

That's all for this issue, thank you for your support and attention!